As integrated circuit (IC) technology continues downsizing to 45 nanometers (nm) and 32 nm feature sizes, planarity and tight defect control are becoming increasingly important. These requirements intensify the challenges faced by suppliers of various chemical-mechanical planarization (CMP) consumables, including pads, slurries, and conditioners. During the conditioning process, it is not sufficient to simply maintain process stability by conditioning the glazed surface of the pad. In addition, the conditioner is also responsible for generating pad texture or topography which greatly influences wafer surface quality. Inappropriate conditioner selection can produce micro-scratches on the polished wafer surface and increase dishing.
Therefore, there is a need for the development of pad conditioners that meet stringent defect requirements, especially for advanced sub-50 nm) technology nodes.